Two terminal current regulator

ABSTRACT

A two terminal current-limiting circuit is in series with the power supply of a circuit to be protected. An increase in load current is accompanied by an increase in voltage across the terminals. A portion of this voltage is applied to a controlling transistor which renders a series transistor less conductive.

United States Patent Michael Scott Fisher Ringoes, NJ. 342,649

Feb. 5, 1964 Nov. 30, 1971 RCA Corporation inventor Appl. No. FiledPatented Assignee TWO TERMINAL CURRENT REGULATOR 22 Claims, 3 DrawingFigs.'

int. Cl G05! 1/58 Field of Search 307/88.5

(l5.2); 323/22 T, 9, 39; 321/] l, 14

[56] References Cited UNITED STATES PATENTS 2.978,630 4/1961 La Tour323/4 3,028,473 4/1962 Dyer..... 219/20 3,182,246 5/1965 Lloyd 323/223,251,951 5/1966 Meewezen 179/81 3,255.402 6/1966 Vollnhals 323/22Primary Examiner-A. D. Pellinen Attorney-Eugene M. Whitacre ABSTRACT: Atwo terminal current-limiting circuit is in series with the power supplyof a circuit to be protected. An increase in load current is accompaniedby an increase in voltage across the terminals. A portion of thisvoltage is applied to a controlling transistor which renders a seriestransistor less conductive.

PATENTEU unvsolan 3.624.490

I N VE NTOR. MIMWZ 5/71? TWO TERMINAL CURRENT REGULATOR In manyelectrical circuit applications it is desirable to provide some form ofcurrent regulation to prevent excessive current flow from a power supplyto a load. Such control of current is of particular importance inhigh-power transistor amplifier circuits, wherein a fault condition,such as a shorted load, may cause the destruction of expensive poweroutput transistors. In many cases, such destruction can take place in amatter of microseconds.

Previous protection devices. such as fuses or mechanicaltype circuitbreakers cannot respond fast enough to provide the desired protection.Furthermore, most types of electrical current limiting circuits limitthe load current at some maximum value. Under many conditions thevoltage applied across the output transistors at sustained values ofhigh current (maximum limited value) causes power dissipation whichdestroys the transistor after a period of time. Such currentlimitingcircuits require regulating devices that have power ratings farexceeding the power to be delivered to the load in order to successfullylimit the current at some maximum value. As a result, a circuit designedto limit the current at a maximum value may become prohibitivelyexpensive.

It is therefore an object of this invention to provide a new andimproved semiconductor two-terminal overload protection circuit.

It is a further object of this invention to provide a semiconductoroverload protection circuit with sufficient speed of response to suddenchanges in current demand to protect semiconductor devices against bothtransient as well as continuous short circuits.

It is also an object of this invention to provide a new and improvedsemiconductor overload protection circuit employing a current-limitingcapable of protecting semiconductor circuits without dissipating a largeamount of power or having a power rating exceeding the power that mustbe delivered to the load.

The current limiting circuit of the present invention is a two-terminalcircuit that may be put in series with the power supply of the circuitto be protected. The invention includes a pair of transistors, oneproviding a series current path between the two terminals and the othercontrolling the series transistor. A portion of the voltage developedacross the two terminals is applied to the controlling transistor. Thecontrolling transistor responds to an increase in voltage across theterminals due to an increase in load current to render the seriestransistor less conductive.

The novel features which are considered to be characteristic of thisinvention are set forth in particularity in the ap pended claims.

The invention itself, however, both as to its organization and method ofoperation will best be understood from the following description whenread in connection with the accompanying drawings in which:

FIG. I. a schematic circuit diagram of a semiconductor overloadprotection circuit embodying the invention;

FIG. 2 is a graph showing the current-voltage response of the circuitshown in FIG. I; and

FIG. 3 is a schematic circuit diagram illustrating the use of a pair oftheprotection circuits of FIG. I to protect a two-power supplysingle-ended push-pull circuit against an overload.

Referring now to the drawings wherein like reference numerals are usedto designate like component in the various FIGS. thereof, andparticularly to FIG. I, the overload protection circuit is showncontaining a power transistor connected in a series circuit between aterminal 14 and a terminal 16. An emitter resistor 12 is connectedbetween the emitter 18 of the transistor 10 and the terminal 14. Theseries circuit is completed by connecting the collector 20 of thetransistor 10 to the terminal 16.

An emitter 22 of a controlling transistor 24 is also connected to theterminal I4 and a collector 26 of the controlling transistor 24 isconnected to a base 28 of the power transistor 10 and to one lead of abiasing resistor 30. The collector cir- 5 junction 33. A base 36 of thecontrolling transistor 24 is coupled to the junction 33 by a diode 38.The anode of the diode 38 is connected to the base 36, and the cathodeof the diode 38 is connected to the junction 33 forming a unidirectionalcurrent path from the base 36 to the junction 33.

Although the present example in FIG. 1 illustrates the use of PNP-typetransistors, the circuit operates substantially as well modified for theuse of NPN transistors. Such a modification requires the reversal of theconnections of the diode 38, and a substitution of the NPN transistorfor the PNP element for element. The operation of the modified circuitis substantially the same if the polarity of the voltage applied to theterminals I4 and I6 is reversed.

The curve in FIG. 2 is a graphic representation of the operation of thecircuit in FIG. 1 as a function of the current flowing between theterminals 14 and 16. The abscissa 40 represents the voltage drop acrossthe terminals 14 and 16 while the ordinate 42 represents the currentflow between the terminals 16 and 14.

The circuit of FIG. 1 can be incorporated into any circuit requiringprotection by connecting the two-terminal device in series with thedirect voltage power supply line to the circuit with the correctpolarity to provide for current flow from terminal 14 to terminal 16 asillustrated in FIG. 1. When connected in this manner, the overloadcircuit fulfills the dual function of protecting the power supplyagainst an overload as well as protecting the connected load.

The circuit operation will be explained with reference to FIG. I, butthe explanation applies as well to a modified circuit withNPN-transistors. The transistor 10 in FIG. I is biased into a saturationthrough the resistor 30 during the normal current drain by the attachedload. The load may be connectedbetween terminal 16 and ground as shown,with the power supply between terminal 14 and ground. The load and powersupply may be interchanged if desired, and if the proper polarities ofconnection are observed. For the designated component values shown inFIG. 1 the circuit is designed for normal current drain of between 0 and3 amps as shown by slope 41, the curve in FIG. 2. The transistor 24during this period of operation is biased to a cutoff condition by thebiasing resistors 32 and 34 and the diode 38. With the transistor 10 issaturation, and the transistor 24 cutoff, these transistors areoperating under the minimum power dissipation conditions during normalcurrent demand.

When a predetermined maximum amount of current is drawn by the attachedload, (which in the present example is 3 amps as shown in FIG. 2), thevoltage drop across terminals 14 and 16 due to the current flow throughthe resistor 12 and the saturated transistor 10. reaches a level atwhich the voltage developed at the junction 33 issuf'ficient to drivethe series combination of the diode 38 and the emitter 22-base 36junction of transistor 24 into conduction. This increased biasingvoltage causes the transistor 24 to conduct thereby increasing thevoltage drop across the resistor 30. The increases voltage drop acrossthe resistor 30 is of a polarity to reduce the conductance of thetransistor 10. As the transistor 10 comes out of saturation, the voltageacross the terminal 16 and 14 increases, thereby again furtherincreasing the voltage on the base 36 of the transistor 24. Aregenerative-type effect takes place until the transistor 10 issubstantially completely cut off and the transistor 24 is saturated fullon. The transitional state between saturation and cutoff of transistor10 is shown by the slope of region 44 of FIG. 2. Once the circuitcurrent conduction has reached the 3 ampere level the controllingtransistor 24 takes control and efiectively instantaneously switches thecircuit through the region 44 into a region of reduced current orprotecting condition 46. This negative slope region 44 accounts for thesensitivity of the overload protection device and enables the device toswitch into the current limiting condition 46 within at least 15microseconds of an applied overload. This is sufficient response toprotect against semiconductor overload conditions.

While the circuit is in the protecting condition 46, only the transistor24 is conducting (fully saturated) while the transistor 10 is completelycut off. While the circuit is in the protecting condition 46. thetransistors again are operating under minimum power dissipation. In theprotecting condition 46, substantially the only current supplied to theload is that which flows through the resistor 30. In the present examplethe resistor 30 has a value of 100 ohms, which for allpractical purposesis high enough to limit the current to a point that can be considered anopen circuit. Once the circuit has reached the overload protectingcondition 46 the circuit remains in this condition until the currentflow to current limiting circuit is cut off. The circuit is notself-resetting and therefore remains in the protecting condition 46indicating a fault occurred even though the fault is subsequentlycorrected. The current-limiting circuit is resettable for normaloperation by completely cutting-off the current to the circuit.

The diode 38, shown connected to the biasing circuit of transistor 24 inFIG. 1, is incorporated into the circuit to provide a delay in reachingthe switching condition and to provide fast switching once the presetcurrent limit is reached. In the present example, the transistor 24(2N408) is a germaniumtype transistor while the diode 38 (lN2858) is asilicon device. The 0.6-0.7 volts forward conduction voltage of thediode 38 provides the delay for the switching time. F urthermore,forward conduction curve of the silicon diode 38 is much sharper thanthe forward conduction curve (V between the emitter 22 and the base 36of the transistor 24 thereby providing the sharp response in slope 44and hence fast switching, once the diode conduction begins. The diode 38may be eliminated and the base 36 of the transistor 24 may bedirectly-connected to the junction 33. The value of the resistors 32 and34 can be adjusted to compensate for the removal of the diode 38 and thecircuit in FIG. I then operates as an overload protecting device butwith a slower response, and more gradual slope in the negativeresistance slope or region 44.

The resistor 12 in FIG. I can also be eliminated and the circuitcontinues to operate as an overload protection device. Under theseconditions, the transistor is not completely turned off unless it is asilicon-type transistor. Again the values of the resistors 32 and 34require adjusting to compensate for the elimination of the resistor 12.The resistor 12, in addition to providing a voltage drop proportional tocurrent between the terminals 14 and 16, provides an added advantage ofallowing the interchangability of the transistor 10 by compensating forthe difference in the gain between various transistors of the same type.

FIG. 3 illustrates the versatility of the overload protection circuit ofFIG. 1 by demonstrating how a pair of these devices can be incorporatedinto a circuit requiring power supplies of both polarities.

The transistors 54 and 56 of FIG. 3 are complementary NPN.PNP-transistors connected for signal ended push-pull operation. Theinput signals are applied across the terminals 58 and 60 and the outputis taken across the terminals- 62 and 64. A circuit of this typerequires power supplies of both polarities 66 and 68 each referenced toground 70. Complete overload protection for this type of circuit canonly be afforded by preventing excessive current flow from either powersupply. This type of current overload can be illustrated by a shortacross a load 72 to ground 70. An overload protection device in serieswith one power supply may protect the circuit against excessive currentflowing through both power supplies or from the connected power supplyto ground but does not protect against the excessive current flowingfrom the unprotected power supply to ground.

As shown in FIG. 3, an overload protection circuit in the dashed block50 protects against excessive current from the positive power supply 66while the circuit in the dashed block 52 protects against excessivecurrent from the negative power supply 68. In each case the sameoverload protection circuit is used in both blocks 50 and 52 byconnecting the circuit for correct current flow between the terminals 14and 16.

The overload protection circuit is self-resetting when in use with aclass B or class C biased-type circuit. In FIG. 3 with zero signal inputacross terminals 58 and 60. the transistors 54 and 56 are cut off. Thetransistors 56 and 54 are switched off and on depending upon thepolarity of the input signal. With an alternating input current signalthe transistors 54 and 56 are cut off in alternate half cycles. Anyoverload introduced into the circuit causing excessive current to groundis reflected automatically through the affected power supply causing theassociated overload protection device to trip to the protectingcondition 46. Since the transistors are cut off at alternate halfcycles, the current through the associated overload protection circuitwill also be cut off at each half cycle automatically resetting theoverload protection circuit for normal operation.

If only a transient current overload had occurred the overloadprotection circuit is automatically reset for normal operation as thetransistors are switched. If the short circuit persists, the overloadcircuit again switches into its protecting condition 46. The cycle keepsrepeating until the fault has been removed.

From the foregoing description it can be seen that overload protectionfor semiconductor circuits can be incorporated into any circuit by theuse of the overload protection circuit of FIG. I. The two-terminaldevice may be inserted in series with the power supply line of thecircuit to be protected. The circuit is designed with regenerativefeedback that is a function of current drawn through it. Thisregenerative feedback allows the circuit to switch from a normaloperating condition to an overload condition with sufficient speed ofresponse to protect the associated semiconductor circuits againsttransient overload. Furthermore, the protection circuit transistorswhile either in the normal or the overload conditions are in a saturatedor a cut off condition, continuously dissipating a minimum amount ofpower thereby being capable of protecting against continuous overloadsas well as transients.

What is claimed is:

l. A two-terminal network comprising:

first and second terminals;

first and second semiconductor devices each having base.

collector and emitter electrodes;

means connecting said first device emitter electrode to said firstterminal;

means connecting said first device collector electrode to said secondterminal;

biasing means connecting said first device base electrode to said secondterminal;

means connecting said second device emitter electrode to said firstterminal;

means connecting said second device collector electrode to said firstsemiconductor base electrode; and

means coupling a portion of a variable direct voltage developed acrosssaid first and second terminals to said second device base electrodewhereby increased conduction of said second device in response to anincreased voltage across said first and second terminals renders saidfirst device less conductive. v

2. A two-terminal network comprising:

first and second terminals;

first and second semiconductor devices each having a base,

a collector and emitter;

a resistor connected between said first device emitter and said fistterminal;

said first device collector being connected to said second terminal;

biasing means connecting said first device base to said second terminal;

said second device emitter being connected to the first terminal;

means connecting said second device collector to said first device base;and

means coupling a portion of a variable direct voltage developed acrosssaid first and second terminals to said second device base wherebyincreased conduction of said second device in response to an increasedvoltage across said first and second terminals renders said first deviceless conductive.

3. A two-terminal network comprising:

first and second terminals;

first and second semiconductor devices each having base,

collector and emitter electrodes;

means connecting said first device emitter electrode to said firstterminal;

means connecting said first device collector electrode to said secondterminal;-

biasing means connecting said first device base electrode to said secondterminal;

means connecting said second device emitter electrode to said firstterminal;

means connecting said second device collector electrode to said firstdevice base electrode;

a voltage divider coupled to said first and second terminals and acrosswhich a variable direct voltage is developed; and

means coupling said voltage divider to said second device base wherebyincreased conduction of said second device in response to an increasedvoltage across said first and second terminals renders said first deviceless conductive.

4. A two-terminal network comprising:

first and second terminals;

first and second semiconductor devices each having a base,

a collector and an emitter;

said first device emitter being connected to said first terminal;

said first device collector being connected to said second terminal;

biasing means connecting said first device base to said second terminal;

said second device emitter being connected to said first terminal;

means coupling said second device collector to said first device base; I

a voltage divider coupled to said first and second terminals and acrosswhich a variable direct voltage is developed; and

mean coupling a diode to said voltage divider and said second devicebase increased whereby conduction of said second device in response toan increased voltage across said first and second terminals renders saidfirst device less conductive.

5. A two-terminal network comprising:

first and second terminals;

first and second semiconductor devices each having a base,

a collector and an emitter;

an impedance element coupled between said first device emitter and saidfirst terminal;

said first device collectorbeing coupled to said second terminal;

biasing means coupling said base of said first device to said secondterminal;

said second device emitter being coupled to said first terminal;

coupling means coupling said second device collector to said firstdevicebase;

a voltage divider coupled to said first and second terminals and acrosswhich a variable direct voltage is developed; and

means coupling said voltage divider to said second device base wherebyincreased conduction of said second device in response to an increasedvoltage across said first and second terminals renders said first deviceless conductive.

6. A two-terminal network comprising:

first and second terminals across which a variable direct voltage isdeveloped;

first and second semiconductor devices each having a base,

collector and emitter;

means connecting said first device emitter to said first terminal;

means connecting said first device collector to said second terminal;

biasing means coupled to said first device base for biasing said firstdevice into saturation;

means coupling said second device emitter to said first terminal;

means coupling said second device collector to said first device base;and

means coupling a portion of the voltage developed across said first andsecond terminals to said second device base so that as said voltagedeveloped across said first and second terminals increases beyond apredetermined level said second device is rendered conductive andrenders said first device nonconductive.

7. A two-terminal network comprising:

first and second terminals across which a variable direct voltage isdeveloped;

first and second semiconductor device each having a base,

collector and emitter;

means connecting said first device emitter to said first terminal;

means connecting said first device collector to said second terminal;

biasing means coupled to said first device base for biasing said firstdevice into saturation;

means connecting said second device emitter to said first I terminal;

means connecting said second device collector to said first devicebiasing means;

means biasing said second device to cutoff, said second device biasingmeans coupling a portion of the voltage developed across said first andsecond terminals to said second device base, so that as said voltagedeveloped across said first and second terminals reaches a predeterminedlevel said second device switches into a saturated condition cutting offsaid first device.

8. A two-terminal network comprising:

first and second terminals across which a variable direct voltage isdeveloped first and second semiconductor devices each having a base,

collector and emitter;

means coupling said first device emitter to said first terminal;

means coupling said first device collector to said second terminal;

biasing means coupled to said first device base for biasing said firstdevice into saturation;

means coupling said second device emitter to said first terminal;

means coupling the second device collector to said first device base;

biasing means biasing said second device to cutoff, said second devicebiasing means coupling a portion of the voltage developed across saidfirst and second terminal to said second device base, so that when saidvoltage developed across said first and second terminals reaches apredetermined level said second device switches into a saturatedcondition cutting off said first device, whereby said second deviceremains in a saturated condition and said first device remains cutoffuntil the current to the two-terminal network is cut off.

9. A current limiting device comprising:

first and second tenninals across which a variable direct voltage isdeveloped;

first and second transistors each having a base, collector and emitter;

a first resistor connected between said first terminal and said firsttransistor emitter;

said first transistor collector being connected to said second terminal;

said second transistor emitter being connected to said first terminal;

said second transistor collector being connected to said firsttransistor base;

a second resistor connected between said first transistor base and saidsecond terminal;

third and fourth resistors connected together forming a junction, saidthird and fourth resistors being connected between said first and secondterminals; and

a diode coupled between the junction of said third and fourth resistorsand said second transistor base.

10. A currentlimiting device comprising:

first and second terminals across which a variable direct voltage isdeveloped;

first and second transistors each having a base, collector and emitter;

first resistor one lead of which is coupled to said first terminal andthe other lead of which is coupled to said emitter of said firsttransistor;

said collector of said first transistor being coupled to said secondterminal;

said emitter of said second transistor being connected to said firstterminal;

said collector of said second transistor being coupled to said firsttransistor base;

a second resistor one lead of which is coupled to said first transistorbase and the other lead of which is coupled to said second terminal;

a voltage divider coupled across said first and second terminals; and

means coupling said voltage divider to said second transistor base.

11. An electric circuit for use with a two-terminal direct currentsource and a two-terminal load, where a first load ter minal isconnected to a first source terminal and where said circuit is connectedbetween the second load terminal and the second source terminal, acrosswhich a variable direct voltage is developed,

a transistor having emitter, base and collector electrodes;

a resistor connected between one of said second load terminal and saidsecond source terminal and said transistor emitter electrode;

said collector electrode being connected to the other of said secondload terminal and said second source terminal;

means coupled to said base electrode for biasing said transistor intosaturation; and

means operable to couple a portion of the voltage developed between saidsecond load and source terminals at a predetermined current to saidtransistor base electrode to cutoff said transistor.

12. An electric circuit for use with a two-terminal direct currentsource and a two-terminal load where a first load terminal is connectedto a first source terminal and where said circuit is connected betweenthe second source terminal and the second load terminal across which avariable direct voltage is developed said electric circuit comprising:

a first transistor having emitter, base and collector electrodes;

said emitter and collector electrodes being respectively connected tosaid second source terminal and said second load terminal;

biasing means coupled to said base electrode for biasing said firsttransistor into saturation;

a second transistor having emitter, base, and collector electrodes;

said second transistor emitter electrode being connected to said firsttransistor emitter electrode;

said second transistor collector electrode being connected to saidbiasing means;

biasing means coupled to said second transistor base electrode forbiasing said second transistor to cutoff;

said second transistor biasing means coupling a portion of the voltagedeveloped across said second source terminal and second load terminal tosaid second transistor base electrode whereby at a predetermined levelsaid voltage switches said second transistor into saturation and saidfirst transistor into cutoff, said circuit remaining in this conditionuntil the current flow between said current source and said load iscutoff.

13. A two-terminal current regulator comprising:

a pair of terminals;

a first semiconductor device having emitter, base and collectorelectrodes;

means connecting the emitter-to-collector current path of said firstdevice between said pair of terminals;

a second semiconductor device having emitter, base and collectorelectrodes;

means including an impedance element connecting the emitter-to-collectorcurrent path of said second device between said pair of terminals in amanner that one terminal of said impedance is connected to the collectorelectrode of said first transistor;

means connecting the other terminal of said impedance element to thebase electrode of said first transistor;

means providing a voltage divider connected between said pair ofterminals and across which a variable direct volt age is developed; and

means connecting the base electrode of said second transistor to saidvoltage divider to maintain said second transistor cutoff until thecurrent between said pair of terminals through the emitter-to-collectorcurrent path of said first transistor reaches a predetermined magnitude.

14. A two-terminal current regulator comprising:

a pair of tenninals across which a variable direct voltage is developed;

a transistor having emitter, base and collector electrodes;

means connecting the emitter-to-collector current path of the transistorbetween said pair of terminals; biasing means coupled to the baseelectrode of said transistor for biasing said transistor in saturation;and

means operable to couple a portion of the voltage developed between saidpair of terminals due to a predetermined current flow between said pairof terminals to said transistor base to render said transistornonconductive,

15. A two-terminal current regulator comprising:

first and second terminals,

first and second transistors, each having emitter, base and collectorelectrodes; means connecting said first transistor emitter electrode tosaid first terminal;

a first resistor connecting said first transistor base electrode to saidsecond terminal;

a direct connection from said first transistor collector electrode tosaid second terminal;

second and third resistors serially connected across said first andsecond terminals;

a direct connection from said second transistor emitter electrode tosaid first terminal;

means connecting said second transistor base electrode to.

the junction of said second and third resistors;

and a direct connection from said second transistor collector electrodeto said first transistor base electrode.

16. A two-terminal current regulator as defined in claim 15 wherein saidfirst transistor emitter electrode connecting means includes a fourthresistor.

17. A two-terminal current regulator as defined in claim 15 wherein saidsecond transistor base electrode connecting means includes a diode.

18. A two-terminal circuit that exhibits a negative currentvoltagecharacteristic region between first and second positive current-voltagecharacteristic regions, comprising first and second terminals forming aninput and output respectively, first, second and third branchesconnected in parallel between said first and second terminals, saidfirst branch comprising a first transistor having its emitter connectedto said first terminal, and means connecting the collector of said firsttransistor to said second terminal, said second branch comprising asecond transistor having it emitter connected to said first terminal,and resistor means connected between the collector of said secondtransistor and said second terminal, said first and second transistorsbeing of the same conductivity type, said third branch comprising aresistive voltage divider having a tap, means connecting the base ofsaid first transistor to the collector of said second transistor, meansconnecting the base of said second transistor to said tap whereby saiddivider provides the sole direct current for said second transistor, asource of voltage, and means applying said voltage between said firstand second terminals, whereby the voltage between said first and secondterminals is variable, the resistances of said voltage divider beingproportioned to hold said second transistor in a cutoff state in a firstrange of voltage between said first and second terminals whereby onlysaid first transistor is conductive, and to bias said second transistorto a conductive state for voltages in a second range between saidterminals above said first range, whereby the collector current flow ofsaid second transistor through said resistor means decreases the basecurrent of said second transistor, and in a portion of said second rangeincreasing voltages between said terminals produce a decrease in thecollector current of said first transistor that is greater than theincrease in collector current of said second transistor.

19. A circuit that exhibits a negative resistance characteristic betweenfirst ans second terminals forming an input and output respectively,comprising first ans second transistors of the same conductivity type,means connecting the emitters of said transistors to said firstterminal, means connecting the collector of said first transistordirectly to said second terminal, means connecting the collector of saidsecond transistor directly to the base of said first transistor, aresistive voltage divider connected between said first and secondterminals, said voltage divider having a tap connected to the base ofsaid second transistor, and resistor means connected between thecollector and emitter of said first transistor, the resistors of saiddivider being proportioned to hold said second transistor cutoff for afirst range of voltages between the emitter and collector s said firsttransistor at which said first transistor is conductive, and to biassaid second transistor to a conductive state at a second range ofvoltages between the emitter and collector of said first transistorabove said first range, whereby second transistor collector currentincreases resulting from increases in emittercollector voltage of saidfirst transistor are less than first transistor collector currentdecreases in a portion of said second range.

20. A two-port circuit that exhibits a negative resistancecharacteristic, comprising a source of potential, a first transistor,means connecting said source between the emitter and collector of saidfirst transistor, a second transistor of the same conductivity type assaid first transistor having its collector connected directly to thebase of said first transistor, means connecting theemitter of saidsecond transistor to the emitter of said first transistor, a resistivevoltage divider connected between the emitter and collector of saidfirst transistor, said divider having a tap connected to the base ofsaid second transistor for providing the sole direct current bias forsaid second transistor, and resistor means connected between thecollector and base of said second transistor, said divider beingproportioned to hold said second transistor cut off for a first range ofemitter-collector voltages of said first transistor during which saidfirst transistor is conductive, and to bias said second transistor to aconductive state for a second range of emitter-collector voltages, ofsaid first transistor above said first range, whereby a negativeresistance characteristic occurs between the emitter and collector ofsaid first transistor during a portion of said second range ofemitter-collector voltages of said first transistor.

21. A circuit that exhibits a negative resistance characteristiccomprising first and second terminals forming an input and outputrespectively, a source of potential, means applying said potentialbetween said first and second terminals, first and second transistors ofthe same conductivity type, means connecting the emitter of said firsttransistor to said first terminal, means connecting the emitter of saidsecond transistor to said first terminal, resistor means having one endconnected to the collector of said first transistor, means connectingthe other end of said resistor means to the base of said firsttransistor and the collector of said second transistor, whereby the onlycurrent flow through said resistor means is the base current of saidfirst transistor and collector current of said second transistor, meansconnecting the collector of said first transistor to said secondterminal, and a resistive voltage divider connected between said firstterminal and the collector of said first transistor, said divider havinga tap providing the sole direct bias for said second transistor, saiddivider being proportioned to hold said second transistor cut off for afirst range of emitter-collector voltages of said first transistorduring which said first transistor is conductive, and to bias saidsecond transistor to a conductive state for a second range ofemitter-collector voltages of said first transistor above said firstrange, whereby a negative resistance characteristic occurs between theemitter and collector of said first transistor during a portion of saidsecond range of emitter-collector voltages of said first transistor.

22. A bistable circuit comprising a negative resistance circuit havingfirst and second terminals, and a source of voltage and an out utimpedance serially connected between said first and seconci terminals,said negative resistance circuit comprising a first transistor, meansconnecting the emitter of said first transistor to said first terminal,means connecting the collector of said first transistor to said secondterminal, a second transistor of the same conductivity type as saidfirst transistor, means connecting the emitter of said second transistorto said first terminal, resistance means connected between the'base andcollector of said first transistor, means connecting the collector ofsaid second transistor to the base of said first transistor, a resistivevoltage divider connected between said first terminal and the collectorof said first transistor, and a tap on said divider connected to thebase of said second transistor.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 490Dated November 30, 1971 Inventoflx) Michael Scott Fisher It is certifiedthat error appears in the above-identified patent and that said LettersPatent are hereby corrected as shown below:

Column 1, line 56, between FIG.

Column 7, line 41, after "developed" insert said electric circuitcomprising:

Signed and sealed this 18th day of July 1972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTI'SCHALK Attesting Officer Commissionerof Patents 1" and "a" insert is F ORM P0-1050(10-69| USCOMM-DC50376-F'B9 .5, GOVERNMENT PRINYING OFF CEl IQQ 0-366-33

1. A two-terminal network comprising: first and second terminals; firstand second semiconductor devices each having base, collector and emitterelectrodes; means connecting said first device emitter electrode to saidfirst terminal; means connecting said first device collector electrodeto said second terminal; biasing means connecting said first device baseelectrode to said second terminal; means connecting said second deviceemitter electrode to said first terminal; means connecting said seconddevice collector electrode to said first semiconductor base electrode;and means coupling a portion of a variable direct voltage developedacross said first and second terminals to said second device baseelectrode whereby increased conduction of said second device in responseto an increased voltage across said first and second terminals renderssaid first device less conductive.
 2. A two-terminal network comprising:first and second terminals; first and second semiconductor devices eachhaving a base, a collector and an emitter; a resistor connected betweensaid first device emitter and said first terminal; said first devicecollector being connected to said second terminal; biasing meansconnecting said first device base to said second terminal; said seconddevice emitter being connected to the first terminal; means connectingsaid second device collector to said first device base; and meanscoupling a portion of a variable direct voltage developed across saidfirst and second terminals to said second device base whereby increasedconduction of said second device in response to an increased voltageacross said first and second terminals renders said first device lessconductive.
 3. A two-terminal network comprising: first and secondterminals; first and second semiconductor devices each having base,collector and emitter electrodes; means connecting said first deviceemitter electrode to said first terminal; means connecting said firstdevice collector electrode to said second terminal; biasing meansconnecting said first device base electrode to said second terminal;means connecting said second device emitter electrode to said firstterminal; means connecting said second device collector electrode tosaid first device base electrode; a voltage divider coupled to saidfirst and second terminals and across which a variable direct voltage isdeveloped; and means coupling said voltage divider to said second devicebase whereby increased conduction of said second device in response toan increased voltage across said first and second terminals renders saidfirst device less conductive.
 4. A two-terminal network comprising:first and second terminals; first and second semiconductor devices eachhaving a base, a collector and an emitter; said first device emitterbeing connected to said first terminal; said first device collectorbeing connected to said second terminal; biasing means connecting saidfirst device base to said second terminal; said second device emitterbeing connected to said first terminal; means coupling said seconddevice collector to said first device base; a voltage divider coupled tosaid first and second terminals and across which a variable directvoltage is developed; and means coupling a diode to said voltage dividerand said second device base increased whereby conduction of said seconddevice in response to an increased voltage across said first and secondterminals renders said first device less conductive.
 5. A two-terminalnetwork comprising: first and second terminals; first and secondsemiconductor devices each having a base, a collector and an emitter; animpedance element coupled between said first device emitter and saidfirst terminal; said first device collector being coupled to said secondterminal; biasing means Coupling said base of said first device to saidsecond terminal; said second device emitter being coupled to said firstterminal; coupling means coupling said second device collector to saidfirst device base; a voltage divider coupled to said first and secondterminals and across which a variable direct voltage is developed; andmeans coupling said voltage divider to said second device base wherebyincreased conduction of said second device in response to an increasedvoltage across said first and second terminals renders said first deviceless conductive.
 6. A two-terminal network comprising: first and secondterminals across which a variable direct voltage is developed; first andsecond semiconductor devices each having a base, collector and emitter;means connecting said first device emitter to said first terminal; meansconnecting said first device collector to said second terminal; biasingmeans coupled to said first device base for biasing said first deviceinto saturation; means coupling said second device emitter to said firstterminal; means coupling said second device collector to said firstdevice base; and means coupling a portion of the voltage developedacross said first and second terminals to said second device base sothat as said voltage developed across said first and second terminalsincreases beyond a predetermined level said second device is renderedconductive and renders said first device nonconductive.
 7. Atwo-terminal network comprising: first and second terminals across whicha variable direct voltage is developed; first and second semiconductordevice each having a base, collector and emitter; means connecting saidfirst device emitter to said first terminal; means connecting said firstdevice collector to said second terminal; biasing means coupled to saidfirst device base for biasing said first device into saturation; meansconnecting said second device emitter to said first terminal; meansconnecting said second device collector to said first device biasingmeans; means biasing said second device to cutoff, said second devicebiasing means coupling a portion of the voltage developed across saidfirst and second terminals to said second device base, so that as saidvoltage developed across said first and second terminals reaches apredetermined level said second device switches into a saturatedcondition cutting off said first device.
 8. A two-terminal networkcomprising: first and second terminals across which a variable directvoltage is developed; first and second semiconductor devices each havinga base, collector and emitter; means coupling said first device emitterto said first terminal; means coupling said first device collector tosaid second terminal; biasing means coupled to said first device basefor biasing said first device into saturation; means coupling saidsecond device emitter to said first terminal; means coupling the seconddevice collector to said first device base; biasing means biasing saidsecond device to cutoff, said second device biasing means coupling aportion of the voltage developed across said first and second terminalto said second device base, so that when said voltage developed acrosssaid first and second terminals reaches a predetermined level saidsecond device switches into a saturated condition cutting off said firstdevice, whereby said second device remains in a saturated condition andsaid first device remains cutoff until the current to the two-terminalnetwork is cut off.
 9. A current limiting device comprising: first andsecond terminals across which a variable direct voltage is developed;first and second transistors each having a base, collector and emitter;a first resistor connected between said first terminal and said firsttransistor emitter; said first transistor collector being connected tosaid second terminal; said second transistor emitter being connected tosaid first terminal; said second transistor collector being connected tosaid first transistor base; a second resistor connected between saidfirst transistor base and said second terminal; third and fourthresistors connected together forming a junction, said third and fourthresistors being connected between said first and second terminals; and adiode coupled between the junction of said third and fourth resistorsand said second transistor base.
 10. A current-limiting devicecomprising: first and second terminals across which a variable directvoltage is developed; first and second transistors each having a base,collector and emitter; first resistor one lead of which is coupled tosaid first terminal and the other lead of which is coupled to saidemitter of said first transistor; said collector of said firsttransistor being coupled to said second terminal; said emitter of saidsecond transistor being connected to said first terminal; said collectorof said second transistor being coupled to said first transistor base; asecond resistor one lead of which is coupled to said first transistorbase and the other lead of which is coupled to said second terminal; avoltage divider coupled across said first and second terminals; andmeans coupling said voltage divider to said second transistor base. 11.An electric circuit for use with a two-terminal direct current sourceand a two-terminal load, where a first load terminal is connected to afirst source terminal and where said circuit is connected between thesecond load terminal and the second source terminal, across which avariable direct voltage is developed, a transistor having emitter, baseand collector electrodes; a resistor connected between one of saidsecond load terminal and said second source terminal and said transistoremitter electrode; said collector electrode being connected to the otherof said second load terminal and said second source terminal; meanscoupled to said base electrode for biasing said transistor intosaturation; and means operable to couple a portion of the voltagedeveloped between said second load and source terminals at apredetermined current to said transistor base electrode to cutoff saidtransistor.
 12. An electric circuit for use with a two-terminal directcurrent source and a two-terminal load where a first load terminal isconnected to a first source terminal and where said circuit is connectedbetween the second source terminal and the second load terminal acrosswhich a variable direct voltage is developed said electric circuitcomprising: a first transistor having emitter, base and collectorelectrodes; said emitter and collector electrodes being respectivelyconnected to said second source terminal and said second load terminal;biasing means coupled to said base electrode for biasing said firsttransistor into saturation; a second transistor having emitter, base,and collector electrodes; said second transistor emitter electrode beingconnected to said first transistor emitter electrode; said secondtransistor collector electrode being connected to said biasing means;biasing means coupled to said second transistor base electrode forbiasing said second transistor to cutoff; said second transistor biasingmeans coupling a portion of the voltage developed across said secondsource terminal and second load terminal to said second transistor baseelectrode whereby at a predetermined level said voltage switches saidsecond transistor into saturation and said first transistor into cutoff,said circuit remaining in this condition until the current flow betweensaid current source and said load is cutoff.
 13. A two-terminal currentregulator comprising: a pair of terminals; a first semiconductor devicehaving emitter, base and collector electrodes; means connecting theemitter-to-collector current path of said first device between said pairof terminals; a second semiconductor device having emitter, base andcollector electrodes; means including an impedance element connectingthe emitter-to-collector current path of said second device between saidpair of terminals in a manner that one terminal of said impedance isconnected to the collector electrode of said first transistor; meansconnecting the other terminal of said impedance element to the baseelectrode of said first transistor; means providing a voltage dividerconnected between said pair of terminals and across which a variabledirect voltage is developed; and means connecting the base electrode ofsaid second transistor to said voltage divider to maintain said secondtransistor cutoff until the current between said pair of terminalsthrough the emitter-to-collector current path of said first transistorreaches a predetermined magnitude.
 14. A two-terminal current regulatorcomprising: a pair of terminals across which a variable direct voltageis developed; a transistor having emitter, base and collectorelectrodes; means connecting the emitter-to-collector current path ofthe transistor between said pair of terminals; biasing means coupled tothe base electrode of said transistor for biasing said transistor intosaturation; and means operable to couple a portion of the voltagedeveloped between said pair of terminals due to a predetermined currentflow between said pair of terminals to said transistor base to rendersaid transistor nonconductive.
 15. A two-terminal current regulatorcomprising: first and second terminals, first and second transistors,each having emitter, base and collector electrodes; means connectingsaid first transistor emitter electrode to said first terminal; a firstresistor connecting said first transistor base electrode to said secondterminal; a direct connection from said first transistor collectorelectrode to said second terminal; second and third resistors seriallyconnected across said first and second terminals; a direct connectionfrom said second transistor emitter electrode to said first terminal;means connecting said second transistor base electrode to the junctionof said second and third resistors; and a direct connection from saidsecond transistor collector electrode to said first transistor baseelectrode.
 16. A two-terminal current regulator as defined in claim 15wherein said first transistor emitter electrode connecting meansincludes a fourth resistor.
 17. A two-terminal current regulator asdefined in claim 15 wherein said second transistor base electrodeconnecting means includes a diode.
 18. A two-terminal circuit thatexhibits a negative current-voltage characteristic region between firstand second positive current-voltage characteristic regions, comprisingfirst and second terminals forming an input and output respectively,first, second and third branches connected in parallel between saidfirst and second terminals, said first branch comprising a firsttransistor having its emitter connected to said first terminal, andmeans connecting the collector of said first transistor to said secondterminal, said second branch comprising a second transistor having itsemitter connected to said first terminal, and resistor means connectedbetween the collector of said second transistor and said secondterminal, said first and second transistors being of the sameconductivity type, said third branch comprising a resistive voltagedivider having a tap, means connecting the base of said first transistorto the collector of said second transistor, means connecting the base ofsaid second transistor to said tap whereby said divider provides thesole direct current for said second transistor, a source of voltage, andmeans applying said voltage between said first and second terminals,whereby the voltage between said first and second terminals is variable,the resistances of said voltage divider being proportioned to hold saidsecond transistor in a cutoff state in a first range of voltage betweensaid first and second terminals whereby only said first transistor isconductive, and to bias said second transistor to a conductive state forvoltages in a second range between said terminals above said firstrange, whereby the collector current flow of said second transistorthrough said resistor means decreases the base current of said secondtransistor, and in a portion of said second range increasing voltagesbetween said terminals produce a decrease in the collector current ofsaid first transistor that is greater than the increase in collectorcurrent of said second transistor.
 19. A circuit that exhibits anegative resistance characteristic between first ans second terminalsforming an input and output respectively, comprising first and secondtransistors of the same conductivity type, means connecting the emittersof said transistors to said first terminal, means connecting thecollector of said first transistor directly to said second terminal,means connecting the collector of said second transistor directly to thebase of said first transistor, a resistive voltage divider connectedbetween said first and second terminals, said voltage divider having atap connected to the base of said second transistor, and resistor meansconnected between the collector and emitter of said first transistor,the resistors of said divider being proportioned to hold said secondtransistor cutoff for a first range of voltages between the emitter andcollector os said first transistor at which said first transistor isconductive, and to bias said second transistor to a conductive state ata second range of voltages between the emitter and collector of saidfirst transistor above said first range, whereby second transistorcollector current increases resulting from increases inemitter-collector voltage of said first transistor are less than firsttransistor collector current decreases in a portion of said secondrange.
 20. A two-port circuit that exhibits a negative resistancecharacteristic, comprising a source of potential, a first transistor,means connecting said source between the emitter and collector of saidfirst transistor, a second transistor of the same conductivity type assaid first transistor having its collector connected directly to thebase of said first transistor, means connecting the emitter of saidsecond transistor to the emitter of said first transistor, a resistivevoltage divider connected between the emitter and collector of saidfirst transistor, said divider having a tap connected to the base ofsaid second transistor for providing the sole direct current bias forsaid second transistor, and resistor means connected between thecollector and base of said second transistor, said divider beingproportioned to hold said second transistor cut off for a first range ofemitter-collector voltages of said first transistor during which saidfirst transistor is conductive, and to bias said second transistor to aconductive state for a second range of emitter-collector voltages, ofsaid first transistor above said first range, whereby a negativeresistance characteristic occurs between the emitter and collector ofsaid first transistor during a portion of said second range ofemitter-collector voltages of said first transistor.
 21. A circuit thatexhibits a negative resistance characteristic comprising first andsecond terminals forming an input and output respectively, a source ofpotential, means applying said potential between said first and secondterminals, first and second transistors of the same conductivity type,means connecting the emitter of said first transistor to said firstterminal, means connecting the emitter of said second transistor to saidfirst terminal, resistor means having one end connected to the collectorof said first transistor, means connecting the other end of saidresistor means to the base of said first transistor and the collector ofsaid second transistor, whereby the only current flow through saidresistor means is the base current of said first transistor andcollector current of said second transistor, means connecting thecollector of said first transistor to said second terminal, and aresistive voltage divider connected between said first terminal and thecollector of said first transistor, said divider having a tap providingthe sole direct bias for said second transistor, said divider beingproportioned to hold said second transistor cut off for a first range ofemitter-collector voltages of said first transistor during which saidfirst transistor is conductive, and to bias said second transistor to aconductive state for a second range of emitter-collector voltages ofsaid first transistor above said first range, whereby a negativeresistance characteristic occurs between the emitter and collector ofsaid first transistor during a portion of said second range ofemitter-collector voltages of said first transistor.
 22. A bistablecircuit comprising a negative resistance circuit having first and secondterminals, and a source of voltage and an output impedance seriallyconnected between said first and second terminals, said negativeresistance circuit comprising a first transistor, means connecting theemitter of said first transistor to said first terminal, meansconnecting the collector of said first transistor to said secondterminal, a second transistor of the same conductivity type as saidfirst transistor, means connecting the emitter of said second transistorto said first terminal, resistance means connected between the base andcollector of said first transistor, means connecting the collector ofsaid second transistor to the base of said first transistor, a resistivevoltage divider connected between said first terminal and the collectorof said first transistor, and a tap on said divider connected to thebase of said second transistor.